JP1 Remotes

Hello.
I'm an IT guy...trying to remember my assembler...its been AWHILE for me.

I'm tinkering with some custom extender logic, and wasn't sure about
how to modify the ram within the code.

so, the way I understand it...the protocol code is copied from EEPROM
into RAM at address FF00 (for a 15-2116).

Is this ram built INTO the CPU or is it external? (maybe in the EEPROM chip?) The processor specs didn't seem to mention any ram at FF00 ?

I'm trying to modify a few bytes...and looking at using the LDC command.
but wasn't sure if it was internal or external (LDC -vs- LDE)

example would be: LDC FF10H,RC0

I'm sure someone has done this before...but didn't see any LDC, LDE in
the 15-2116 extender's code.


:Pat

ngtw16a wrote:Hello.
I'm an IT guy...trying to remember my assembler...its been AWHILE for me.

I'm tinkering with some custom extender logic, and wasn't sure about
how to modify the ram within the code.

Humbling isn't it. EEPROM extenders are very difficult to write.

You might find this thread of interest.
http://www.hifi-remote.com/forums/viewtopic.php?t=7637

I don't have a clue as to where the RAM is, although I know it is not in the EEPROM. Once I finished with the Cinema 7, I moved on to the JP1.2 Flash remotes which were much easier to extend.

I moved this thread to the extender forum.

On the JP1 remotes yes the protocol is copied from the E2 to RAM before being executed since the E2 is connected to the processor by a serial bus. The RAM varies depending on which variant of the S3C8 processor you're talking about, but generally FF00 is a good place to start

On the JP1.3 remotes the protocol is not copied since the E2 is inside the processor chip and is directly accessible so no need to do that extra work.

Also, now back from traveling so I can try to clarify the LDC and LDE instructions

S3C80 processors had an interface for external memory to augment the amount that was on board. Remember they only had ROM and all of the EEPROM stuff was done through a serial interface into RAM.

The S3F80 flash based processors have no external interface to allow you to add on more memory. Thus the LDE instruction really isn't there.

The assembler syntax for the instructions is the same and the assembler puts in a bit (I think in bit 0 since the addresses for the instruction are word aligned) that will indicate which memory, internal or external)

So on a JP1.3 remote the LDC is really the only instruction.

The flash based processors have on board flash and RAM. the flash memory holds both the "code" for the remote and the settings (aka the "E2" area). RAM is used for scratch pad work and the stack used in calling/returning and things like that.

"Program Memory" is from $0000 to $FFFE, on all of the processor variants I know RAM starts at FE80 or FF00, the rest is Flash.