JP1 Remotes

[HamburgerHelper1]

Since pin 2 goes to the processor and the common connection for the transport keys
I have the cable connected the correct direction I held down rew,play ffd and pause
and attempted raw download
Remote responded with the 2 blinks and back light on/off just like when i had the cable reversed
_________________
Randy

[3FG]

[HamburgerHelper1]

Since Graham is getting the same results as I am I assume i am connecting the cable correctly
Hard to see in these pics but in the pic showing circuit trace the lower left pin that i am calling pin 2 connects to processor and to transport keys
that is why i thought UEI might have a secret key press for programming


_________________
Randy

[HamburgerHelper1]

I did have my cable on wrong when holding buttons so it does not respond when holding keys after all
_________________
Randy

[mathdon]

[HamburgerHelper1]

I zipped up some pics and put them in Diagnosis section
Hopefully these are clear enough I had more pics but it was over file size limit
when I attempted upload


http://www.hifi-remote.com/forums/dload.php?action=file&file_id=26882
_________________
Randy

[3FG]

The picture of the brown side of the PCB has pin 1 labeled. It is top right in that picture, so it will be top left in the green side pictures, just as mathdon had deduced.

[mathdon]

I have spent a considerable amount of time studying the wiring of the URC-2060 from the images that Randy has kindly supplied and concluded that there is no significant difference, from our point of view, from the standard wiring of a JP1.4 remote. I see from his images that the PCB does label the 6-pin connector as JP1.4, so that removes any doubt as to how UEI regards this remote. All six pins are connected to the 24-pin processor, which I believe to be an S3F80P5X (or very similar), with our pin number and the processor datasheet label as follows:

1 = 3.3V, 2 = nRESET/P0.2/INT2, 3 = Vss, 4 = SDAT/P0.0/INT0, 5 = TEST, 6 = SCLK/P0.1/INT1.

Tommy's examination of an OARI06G, also JP1.4, found a 44-pin processor which he identfied as an S3F80KB. I can find no such processor and take it to be an S3F80JB which Rob has posted as the JP1.3 processor. He has the following connections for the 6-pin connector, with the datasheet labels of that processor:

1 = 3.3V, 2 = nRESET, 3 = Vss, 4 = P3.0/TOPWM/T0CAP/SDAT, 5 = TEST, 6 = P3.1/REM/SCLK.

All this seems to match. Both datasheets say that TEST is normally set Low (0), setting it to High (1) puts the remote in TOOL mode in which the flash memory can be programmed by an external programmer through a serial interface using SDAT (pin 4) and SCLK (pin 6). In normal mode, these pins are available as P0.0/P0.1 or P3.0/P3.1 programmable I/O pins which we connect as TXD and RXD. Both processors have pin 2 available as nRESET, connected to RTS in our cables.

So for a long time I thought all was well and the remote should be programmable as any other JP1.4 remote. There was just one minor problem that puzzled me. This was the number of pins of the S3F80P5X that were connected in the remote, which was 23 of its 24 pins. The ones not used by the 6-pin connector are given on the datasheet as

Xin, Xout which are system clock input and output pins,
P0.3 - P0.7, P1.0 - P1.7 which are general I/O pins,
P2.0 which is a further general I/O pin,
P3.0 and P3.1 which are I/O pins with high current drive capability.

These are 18 pins of which only 17 appear to be allocated because of the total of 23 in use. Xin and Xout are connected to an external crystal, P3.0 and P3.1 appear to be connected to the IR LED and the LED on the Cable Power key. The backlight LEDs (many of them) need one pin, which may be P2.0. All LEDs are connected to GND (Vss) for their second pin.

This leaves P0.3 - P0.7 and P1.0 - P1.7 available for the keypad matrix. There are 40 keys, probably set as a 5 x 8 matrix, so 13 pins for the matrix and 13 pins are available, using all 24 pins. BUT ONLY 23 PINS ARE CONNECTED IN THE REMOTE! What is going on?

Unfortunately I have the solution. The one disparity between the 6-pin connectors in the two processors is that pin 2 is purely nRESET in the S3F80JB but has alternative uses as nRESET/P0.2/INT2 in the S3F80P5X. Careful reading of the datasheet shows that the nRESET/P0.2/INT2 pin acts as nRESET only in TOOL mode. If you look at the datasheet chapters on RESET for the two processors, the S3F80JB lists six different system reset sources, that for the S3F80P5X lists only five. The lists are the same apart from the one missing from the S3F80P5X, which is the External Reset Pin (nRESET). The only place nRESET/P0.2/INT2 is mentioned as nRESET is in the chapter on programming the flash memory in TOOL mode. So in normal mode it acts as another general I/O output pin P0.2, giving 14 pins P0.2 - P0.7 and P1.0 - P1.7 available for the 13 needed for the keypad matrix, so needing only 23 connections in all to the processor.

Puzzle resolved but the solution is that this remote does not have the ability to modify the flash memory externally in normal mode. The existing firmware can modify it so that the E2 area can function as it does in any other JP1.4 remote, but we cannot do so. Perhaps this should not be a surprise, as the overview at the start of the datasheet shows that this processor has only 18kb of flash, compared with the 64kb of the S3F80JB.
_________________
Graham

[HamburgerHelper1]

[Tiku]

mathdon
Hi mathdon you once said that you have experties in jp1.4 remote please kindly make rdf and maps for this remote as i desperately need remote for my personal use
http://www.hifi-remote.com/forums/dload.php?action=file&file_id=26893